Article ID: 000086010 Content Type: Troubleshooting Last Reviewed: 03/23/2020

Why my Nios® II Simple Socket Server (RGMII) design example Ethernet link is down when run on Intel FPGA Development Kits with MARVELL PHY?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Nios® II Embedded Design Suite (EDS)
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in Nios® II Software Build Tool, the default settings for Nios® II Simple Socket Server (RMII) template is not targeted to MARVELL PHY, which resulted in wrong PHY configurations causing Ethernet link down. This problem is observed in Nios® II SBT version 17.1 onwards.

    Resolution

    To work around this problem the user is required to modify below parameters in template to enable MARVELL PHY RGMII configurations.

     

    Browse to project directory: ../software/<project_name>/tse_my_system.c

     

    Step 1. Uncomment the next definition:

     

    /* if using marvell phy and you want rgmii mode, uncomment this define */

    #define SET_MARVELL_RGMII_MODE //uncomment this definition to enable RGMII

    #ifdef SET_MARVELL_RGMII_MODE

       #define ADDITIONAL_PHY_CFG  &marvell_cfg_rgmii

    #else

       #define ADDITIONAL_PHY_CFG  0

    #endif 

     

     

    Step 2. Find the definition "ifdef DESCRIPTOR MEMORY BASE" and verify the first argument from function TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO to be declared as "ETH_TSE" and not as "TSE_0_TSE"

    As shown in the next code portion:

     

    #ifdef DESCRIPTOR_MEMORY_BASE

    alt_tse_system_info tse_mac_device[MAXNETS] = {

    TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(ETH_TSE, 0, TSE_0_DMA_TX, TSE_0_DMA_RX, TSE_PHY_AUTO_ADDRESS, ADDITIONAL_PHY_CFG, DESCRIPTOR_MEMORY)

         

    };

    Related Products

    This article applies to 2 products

    Intel® Cyclone®
    Intel® MAX® CPLDs and FPGAs

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