Article ID: 000086010 Content Type: Troubleshooting Last Reviewed: 06/20/2025

Why is my Nios® II Simple Socket Server (RGMII) design example Ethernet link down when running on Intel FPGA Development Kits with MARVELL PHY?

Environment

    Intel® Quartus® Prime Design Software
    Nios® II Embedded Design Suite (EDS)
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Description

Due to a problem in the Nios® II Software Build Tool, the default settings for the Nios® II Simple Socket Server (RMII) template are not targeted to MARVELL PHY. This resulted in wrong PHY configurations, causing the Ethernet link to go down.

This problem is observed in Nios® II SBT of Quartus® Prime Pro and Standard versions 17.1 onwards.

Resolution

To work around this problem the user is required to modify the below parameters in the template to enable MARVELL PHY RGMII configurations.

Browse to project directory: ../software/<project_name>/tse_my_system.c

 

Step 1. Uncomment the next definition:

/* if using Marvell phy and you want rgmii mode, uncomment this define */

#define SET_MARVELL_RGMII_MODE //uncomment this definition to enable RGMII

#ifdef SET_MARVELL_RGMII_MODE

   #define ADDITIONAL_PHY_CFG  &marvell_cfg_rgmii

#else

   #define ADDITIONAL_PHY_CFG  0

#endif 

 

Step 2. Find the definition "ifdef DESCRIPTOR MEMORY BASE" and verify the first argument from function TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO to be declared as "ETH_TSE" and not as "TSE_0_TSE"

As shown in the next code portion:

#ifdef DESCRIPTOR_MEMORY_BASE

alt_tse_system_info tse_mac_device[MAXNETS] = {

TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(ETH_TSE, 0, TSE_0_DMA_TX, TSE_0_DMA_RX, TSE_PHY_AUTO_ADDRESS, ADDITIONAL_PHY_CFG, DESCRIPTOR_MEMORY)

};

Related Products

This article applies to 12 products

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Intel® MAX® 10 FPGAs

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