A non-unate timing edge is a clock signal that passes through some sort of block that does not maintain the direction of the edge.
Normal clock signals that are routed to registers through logic are unate, this means that a rising edge going into the logic can only cause a rising edge on the output of the logic and a falling edge going into the logic can only cause a falling edge on the output.
Examples of unate functions are AND gates, OR gates and the data input to a mux.
Examples of non-unate functions are XOR gates and the select input to a mux.
Clocks should only be routed through unate functions otherwise the clock could be phase shifted by 180° or the frequency doubled. The Timing Analyzer bases its analysis on the clock not being inverted and issues a warning when non-unate functions are detected.