Article ID: 000085982 Content Type: Product Information & Documentation Last Reviewed: 08/28/2013

How should I manage the TAG field for Non-Posted accesses with PCIe Avalon Memory-Mapped (Avalon-MM) interface?

Environment

  • PCI Express
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Hard IP for PCI Express® with Avalon-MM interface requires the TAG field to be set as shown below for Non-Posted accesses. 

    TAG = 0x00 - 0x07 : Txs Slave Port

    TAG = 0x08 - 0x0F : Reserved

    TAG = 0x10 - 0x1F : CRA Slave Port

     For Posted accesses, there is no requirement.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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