Article ID: 000085915 Content Type: Troubleshooting Last Reviewed: 01/01/2015

What is the default Local-to-Memory address mapping in the HPS SDRAM controller?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    By default, the Local-to-Memory Address Mapping option when using the HPS SDRAM controller is CHIP-ROW-BANK-COL. This is the Bank Interleave Without Chip Select Interleave option described in Chapter 4  Functional Description - HPS Memory Controller of the EMIF handbook.

    Resolution

    This mapping option is planned to be enhanced in a future version of the Quartus® II software.

    Related Products

    This article applies to 4 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs
    Arria® V GX FPGA
    Cyclone® V GX FPGA

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