Article ID: 000085891 Content Type: Troubleshooting Last Reviewed: 05/04/2015

False Timing Failures in QDR-IV Interfaces on Arria 10 Devices

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    This problem affects QDR-IV interfaces on Arria 10 devices.

    The following I/O timing failures are likely to be reported:

    • DK versus CK timing is likely to fail, because the current timing model assumes that DK/CK calibration is not performed, but in reality DK/CK calibration is performed.
    • Write timing is likely to fail, because the current timing model is incorrect.

    The two timing failures described above are false, and can be ignored.

    Resolution

    There is no workaround for this issue.

    This issue is fixed in version 15.0.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.