Article ID: 000085881 Content Type: Troubleshooting Last Reviewed: 11/18/2024

Why can't encrypted Verilog HDL source code be synthesized?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 17.1 and earlier,  you may see error messages when you synthesize the encrypted Verilog HDL file. This problem occurs when the file is added in the GUI.

    Resolution

    You can work around this problem by adding encrypted files in .qsf (Quartus Settings File) manually shown as below.

    set_global_assignment -name VERILOG_FILE <file name>.vp

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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