Due to a problem in the Intel® Quartus® Prime Pro Edition Software, you might see incorrect old data behaviour for read-during-write operations when new data is expected.
This problem only affects the simulation behaviour for Dual Port RAM Intel® FPGA IP with the following configuration for Intel® Stratix® 10 devices and Intel® Agilex™ devices :
- RAM block type is MLAB
- Read address is unregistered
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.