Article ID: 000085866 Content Type: Troubleshooting Last Reviewed: 09/18/2017

Why do I get error “either synchronous clear option or clock enable option can be chose at the same time” in Platform Designer generation with Stratix 10

Environment

  • Intel® Quartus® Prime Pro Edition
  • Shift Register (RAM-based) Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro software version 17.1 with Stratix® 10 device, you may see the Shift Register (RAM Based) IP Parameter Editor Pro error out message mentioned above in the Platform Designer generation. This happened whenever you try to instantiate both synchronous clear port and clock enable port together.

    Resolution

    To work around the problem, disable either the synchronous clear port or the clock enable port.

    This restriction will be lifted in a future release of the Quartus Prime Pro software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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