Description
Due to a problem in the Quartus® Prime Pro Edition Software version 17.1 with Stratix® 10 device, you might see the Shift Register (RAM Based) IP parameter editor error message mentioned above in the Platform Designer generation. This happened whenever you try to instantiate both the synchronous clear port and the clock enable port together.
Resolution
To work around the problem, disable either the synchronous clear port or the clock enable port.