Article ID: 000085845 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the PLL fail to switch to the secondary clock in automatic clock switchover (manual override) mode when the clkswitch signal remains high?

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When the clkswitch signal goes high, it overrides the automatic clock switchover function. As long as the clkswitch signal is high, further clock switchover action is disabled. You must bring the clkswitch signal back to low again to initiate another clock switchover event in future.

     

    This applies to all Stratix®, Cyclone® and Arria® device families.

    Related Products

    This article applies to 12 products

    Stratix® III FPGAs
    Stratix® II FPGAs
    Stratix® FPGAs
    MAX® V CPLDs
    MAX® II CPLDs
    MAX® 9000 CPLD
    Cyclone® IV FPGAs
    Cyclone® III FPGAs
    Cyclone® FPGAs
    Arria® GX FPGA
    Apex™ 20K
    Acex® 1K

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