Article ID: 000085834 Content Type: Error Messages Last Reviewed: 11/19/2013

Critical Warning: *_p0_pin_map.tcl: Failed to find PLL clock for pins *:s0|*:sequencer_scc_mgr_inst|scc_state_curr.STATE_SCC_IDLE

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You will see this critical warning message if you compile DDR3 Controller with UniPHY with the following assignment. In this case, the Quartus® II software cannot find pll_config_clock.

set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES OFF

The Quartus II software will look for *:s0|*:sequencer_scc_mgr_inst|scc_state_curr.STATE_SCC_IDLE to search pll_config_clock. The state will disappear if you disallow state machine generation thus the Quartus II software cannot find the clock.

Resolution

To avoid this critical warning message, you can remove the assignment or you can allow state machine generation by editing the *_p0_pin_map.tcl file like below.

[Before] set pins(config_ck_pins) *:|*:s0|*:sequencer_scc_mgr_inst|scc_state_curr.STATE_SCC_IDLE

[After] set pins(config_ck_pins) *:|*:s0|*:sequencer_scc_mgr_inst|scc_state_curr[0]

Related Products

This article applies to 11 products

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Stratix® IV GX FPGA
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