Description
You can convert a VWF into an HDL testbench file using the Export command (File menu). Select Verilog HDL or VHDL in the Save as type list.
The new file will have the extension .vt or .vht for Verilog HDL or VHDL respectively. Use this testbench file to perform your functional or gate-level timing simulation in the third-party simulation tool.
For information on simulating your design in a third-party simulation tool, refer to the Simulation section in Volume 2 of the Quartus II Handbook, or the documentation for your simulation tool.