Issue 335051: Clock Networks and PLLs in Arria 10 Devices, Version 2015.11.02
Under the Dedicated Clock Input Pins description on page 4-11, it states that:
The dedicated clock input pins can be either differential clocks or single-ended clocks. When you use the dedicated clock input pins as single-ended clock inputs, only the following pins have dedicated
connections to the PLL:
• fPLL—REFCLK_GXB[L,R][1:4][C,D,E,F,G,H,I,J]_CH[B,T]p
• I/O PLL—CLK_[2,3][A..L]_[0,1][p,n]
This statement is incorrect. fPLL—REFCLK_GXB pin only offer differential clock input support.
The Arria 10 device handbook will be updated with the following statement:
The dedicated clock input pins can be either differential clocks or single-ended clocks. When you use the dedicated clock input pins as single-ended clock inputs, only the following pins have dedicated
connections to the PLL:
• I/O PLL—CLK_[2,3][A..L]_[0,1][p,n]
Issue 326004: Configuration, Design Security, and Remote System Upgrades in Arria 10 Devices, Version 2015.06.15
Under the CLKUSR description on page 7-3, it states that:
“If you are using the CLKUSR pin for calibration, you can only use DCLK for device initialization after the CONF_DONE is asserted for PS and FPP configuration schemes.”
This statement is incorrect. You can use either DCLK or the Internal Oscillator for device initialization phase in Passive Serial (PS) and Fast Passive Parallel (FPP) configuration schemes. The Arria 10 device handbook will be updated with the following statement:
If you are using the CLKUSR pin for calibration, you can use either DCLK or the Internal Oscillator for device initialization after the CONF_DONE is asserted for PS and FPP configuration schemes.
Resolved Issues :
Issue 377441: Power Management in Arria 10, version 2015.12.16
In the Voltage Sensor section, the Voltage Sensor Transfer Function for the Unipolar Mode was mistakenly removed.
The Voltage Sensor Transfer Function for the Unipolar Mode is as follows:
0.000mV = 000, 0.305mV = 001, 0.610mV = 002, 0.915mV = 003, ... 1249.6mV = FFE, 1250mV = FFF
This issue has been fixed in Power Management in Arria 10, version 2016.06.13.
Issue 233280: Booting and Configuration, Chapter 26 in Arria 10 Devices, Version 2014.08.18
In Appendix A on page A-5, it states that :
"If the FPGA boot fuse is not blown, the clock setting (CSEL) pins are used to configure the main PLL and peripheral PLL."
This statement is incorrect. Arria 10 devices do not have CSEL pins.
Issue 229016: Configuration, Design Security, and Remote System Upgrades in Arria 10 Devices, Version 2014.08.18
Table 7-4 states that the nIO_PULLUP pin is powered by VCCPGM.
This is incorrect. The nIO_PULLUP pin is actually powered by VCC.
Issue 299562 : Power Management in Arria 10 Devices, Version 2015.05.15
Figure 10-14: ADC Transfer Function is incorrect. It does not correctly reflect the transfer function to calculate the temperature from tempout[9:0], which is shown below :
Temperature = {(AxC)÷1024} - B
Where:
• A = 708
• B = 273
• C = decimal value of tempout[9..0]
Use the transfer function equation above to derive the temperature reading. The figure will be corrected in a future revision of the handbook.