Article ID: 000085531 Content Type: Troubleshooting Last Reviewed: 07/08/2014

Why do I see a mismatch between the IBIS simulation model and the actual hardware measurement for the read DQ waveform when using the HPS external memory interface?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description When comparing the DQ waveforms, you may notice that the measured steady-state read waveform amplitude exceeds the expected value simulated by the IBIS model. This is due to an adjustment of the Rt termination value by the Quartus® II software where the equivalent resistance is higher than expected.
    Resolution

     

    Related Products

    This article applies to 5 products

    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA

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