Article ID: 000085471 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does TimeQuest Timing Analyzer in Quartus II software versions 7.1 SP1 and beyond report several of the reset and serial loopback ports on high speed transceivers on Stratix II GX devices as unconstrained paths in red?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Quartus® II software versions 7.1SP1 and beyond do not constraint the following reset and serial loopback ports on the ALTGX/ALT2GXB high speed transceivers, hence reporting the unconstrained paths.

    • gxb_powerdown
    • tx_digitalreset
    • rx_digitalreset
    • rx_analogreset
    • rx_seriallpbken
    Resolution

    Manually add the constraints in the Synopsys Design Constraints (.sdc) file for TimeQuest to analyze these paths. Instructions to manually add the constraints to the .sdc file are available in the Stratix II GX Device Handbook (PDF).

    Related Products

    This article applies to 1 products

    Stratix® II GX FPGA

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