How do I enable SKP Ordered Set Detection logic in the Intel® Arria® 10 Hard IP core for PCI Express?

Beginning with the Intel® Quartus® Prime Software v15.1.2, you can enable SKP Ordered Set detection logic in the Intel® Arria® 10 Hard IP for PCI Express.

To enable the SKP Ordered Set detection logic, follow these steps:

1.    Open the IP GUI.
2.    Right click on the Intel® Arria® 10 Hard IP for PCI Express banner and select Show Hidden Parameters.
3.    Scroll down until you see the enable_skp_det parameter and enter "1".
4.    Do not modify any other hidden parameters.
5.    Select Generate HDL.

The SKP detection logic file skp_det_g3.v will be included in your Intel® Quartus® Prime Software file list for compilation.

You can monitor the skp_os signal from the IP core top-level interface. skp_os will assert any time scrambled data exactly matches a SKP pattern when in Gen3 speed.

Erroneous Skip Ordered Sets will cause the IP core to enter the recovery state. Other possible causes for entering recovery are, a high bit error rate (BER) or excessive reference clock parts per million (ppm) difference.

For additional details on the SKP Ordered Set issue, see "Why does the Intel® Hard IP for PCI Express* in Gen3 configurations, periodically transition from the L0 LTSSM state to the Recovery state then back again?".