Critical Issue
Description
If you generate a Verilog HDL model for a CPRI IP core variation with a data rate of 4.915 Gbps that targets an Arria II device and transfers data through 18 or more enabled antenna/carrier interfaces (channels), the IP core drops data on the eighteenth channel in simulation.
Resolution
This issue has no workaround. If you must configure a variation with 18 or more antenna/carrier interfaces, generate and simulate a VHDL model instead of a Verilog HDL model for these CPRI IP core variations,.