Article ID: 000085259 Content Type: Troubleshooting Last Reviewed: 01/18/2013

SDC Constraint Ignored during Quartus Compilation for Stratix V Triple Speed Ethernet Design with IEEE1588 Option

Environment

  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    During Quartus compilation of the triple speed ethernet design with the IEEE1588 option enabled, there is a warning in the generated fit.rpt regarding the filter on line 443 in "<tse_instance_name>_constraints.sdc" being ignored.

    The filter was ignored because the lines "*|inst_stratixv_hssi_8g_tx_pcs|wys|clkout" and "*|inst_stratixv_hssi_8g_rx_pcs|wys|clocktopld" were not matched with a clock.

    This issue will cause uncommon behavior for the data path in hardware.

    This issue affects the triple speed ethernet with the IEEE1588 option enabled in ACDS 12.1 of the Stratix V device.

    Resolution

    Modify the generated "<tse_instance_name>_constraints.sdc". This sdc file is generated by Qsys and is located at: <working_directory>/<qsys_design_name>/synthesis/submodules Search for the keyword "inst_stratixv_hssi_8g_rx_pcs" on line 463 and replace it with "inst_sv_hssi_8g_rx_pcs". Search for the keyword "inst_stratixv_hssi_8g_tx_pcs" on line 472 and replace it with "inst_sv_hssi_8g_tx_pcs".

    This issue will be fixed in ACDS 12.1sp1.�

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.