Article ID: 000085227 Content Type: Troubleshooting Last Reviewed: 12/17/2014

Why can I assign more than a 32-bit data width to the Arria V Hard Memory Controller ?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Although the Arria® V handbook states that the A1, A3, A5 and A7 devices have the capability to support up to a 32-bit width controller on top or bottom edges, the Quartus® II software incorrectly allows you to implement a 40-bit controller without an error message.

 

Resolution This issue is scheduled to be fixed in a future release of the Quartus II software.

Related Products

This article applies to 5 products

Arria® V GX FPGA
Arria® V GT FPGA
Arria® V GZ FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA

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