Article ID: 000085173 Content Type: Troubleshooting Last Reviewed: 09/28/2015

Do Altera Devices support floating LVDS input pins?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The following Altera® device families support floating LVDS input pins:

Stratix® - series beginning with Stratix III devices

HardCopy® - series beginning with HardCopy III devices

Arria® - series beginning with Arria II GX devices

Cyclone® - series beginning with Cyclone V devices

However a 100ohm differential resistance must be applied across the P and N leg of the LVDS receiver.  Internal termination can be used if available for the device family. 

There is no damage if the LVDS input is left floating from an undriven trace or card that is unplugged. However, you need to consider the following:

Floating inputs will cause unknown switching activity leading to noise injected at the receiver and higher current consumption, all of which is design dependent and cannot be specified by Altera. It is then recommended to use external biasing schemes if the noise injection and increased current requirements are undesirable.

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This article applies to 27 products

Cyclone® V GT FPGA
Cyclone® III FPGAs
Stratix® V GX FPGA
Cyclone® IV GX FPGA
Cyclone® V GX FPGA
Arria® V GZ FPGA
Stratix® V GS FPGA
Arria® V GX FPGA
Stratix® V GT FPGA
Arria® V GT FPGA
Stratix® IV GX FPGA
Stratix® III FPGAs
Arria® II GX FPGA
Arria® II GZ FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
HardCopy™ III ASIC Devices
Cyclone® V SX SoC FPGA
Cyclone® V ST SoC FPGA
HardCopy™ IV GX ASIC Devices
Cyclone® V SE SoC FPGA
Cyclone® IV E FPGA
Arria® V SX SoC FPGA
Arria® V ST SoC FPGA
HardCopy™ IV E ASIC Devices
Stratix® IV E FPGA
Stratix® IV GT FPGA

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