Description
If you are configuring a Stratix® V ES device with the PFL via a FPP configuration scheme using the Quartus® II software versions 12.0 SP1 or 12.0 SP2, you will see that the "pfl_flash_access_request" signal in the PFL megafunction will be asserted when it starts to access the flash device, but will never de-assert after the FPGA configuration is completed.
Resolution
This is fixed in the Quartus II software version 12.1.