Article ID: 000084847 Content Type: Troubleshooting Last Reviewed: 05/05/2013

Why do reads from my Altera PLL Reconfig megafunction fail?

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When reads are performed from the Avalon®-MM slave port on the Altera® PLL Reconfig megafunction,  the mgmt_waitrequest is not asserted correctly as specified in the Avalon Interface Specification (PDF) which will lead to the Avalon-MM master reading the incorrect data.

Resolution

A patch is available for Quartus® II 12.0sp2, 2.dp9d, which may be downloaded from the link below.

This patch must be installed after installing the dp9 patch available from the related solution "How do I address known software issues for Stratix® V, Arria® V and Cyclone® V devices in the Quartus II software version 12.0sp2?"

Related articles

Related Products

This article applies to 15 products

Arria® V SX SoC FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.