Article ID: 000084779 Content Type: Troubleshooting Last Reviewed: 05/13/2014

What are the recommended rise and fall time specifications for Altera® devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

All newer Altera device families do not have rise or fall time specifications in the datasheets. Refer to the Input Signal Edge Rate Guidance (PDF) White Paper. 

Holding the transistors in the linear region will cause higher than normal current draw but will not cause damage to the device.

When the input clock edge is slow, it may pick up too much switching noise on the board and on the device such that there might be potential signal integrity issues, such as false triggering due to excessive noise on the slow edge of the clock.

When the clock edge is fast, the noise energy picked up by the clock will not be strong enough to cause a logic problem such as false triggering. The maximum rise/fall time for clocks are application dependent.

Related Products

This article applies to 1 products

Stratix® FPGAs

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