Article ID: 000084772 Content Type: Error Messages Last Reviewed: 08/04/2023

Error (177021): The external clock driver <altclkctrl instance name> sd1 cannot have an ENA_REGISTER_MODE setting of double reg

Environment

    Quartus® II Subscription Edition
    ALTCLKCTRL Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You will see this error message in the Quartus® II software when using the ALTCLKCTRL mega function set for the external path and the 'ena' port. This affects Stratix® V, Arria® V, and Cyclone® V device families.

The only supported legal setting for How do you want to register the 'ena' port is the "falling edge of the input clock." However, due to a bug in the Quartus II software up to version 13.0 SP1, you will receive the following error during design compilation when using this option in the ALTCLKCTRL mega function:

Error (15845): Illegal value "falling edge" for ena_register_mode parameter in Clock Enable Block "<altclkctrl instance name> sd1" -- value must be double register when the ena input is used, and the clock type is "External Clock Output".

Resolution

If you require using an ALTCLKCTRL mega function set for external path and \'ena\' port in the affected device families, contact mySupport and provide the following reference number for a workaround: rd08082013_561.

This problem is fixed in Intel® Quartus® 13.1.

Related Products

This article applies to 15 products

Cyclone® V SX SoC FPGA
Stratix® V E FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Cyclone® V SE SoC FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA

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