Article ID: 000084757 Content Type: Troubleshooting Last Reviewed: 03/17/2023

Is there a known problem with Cyclone® III or Cyclone® IV devices if a user reset is deasserted before the device has entered user mode?

Environment

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Description

Due to a known problem with Cyclone® III and Cyclone® IV devices, unexpected register output behaviour might be caused when a user reset is deassserted before the device enters the user mode.

 

 

Resolution

To avoid this problem, Intel recommends that you deassert user logic reset after the device has entered user mode, or enable the clock source to your registered logic after the device has entered user mode.

The INIT_DONE signal can be used to indicate that the device has entered the user mode. If the INIT_DONE signal is not enabled, refer to the tCD2UM (CONF_DONE high to user mode) parameter in the device handbook.

 

Related Products

This article applies to 4 products

Cyclone® III FPGAs
Cyclone® III LS FPGA
Cyclone® IV E FPGA
Cyclone® IV GX FPGA