If you attempt to access a reserved register in the Low Latency 40-100GbE IP core through its Avalon-MM control and status interface, the transaction might not complete. More precisely, the transaction completes with a meaningless value if you attempt to access a Reserved register in an address range associated with an IP core module, but does not return data and hangs for both read and write accesses for all other reserved register addresses.
This issue has no workaround. Ensure that you only attempt to access the defined registers listed in the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide.
This issue is fixed in version 14.1 of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore function.