Article ID: 000084664 Content Type: Troubleshooting Last Reviewed: 04/17/2013

What is the minimum pulse width for the Hard Processor System cold and warm resets (nPOR, nRST) in Cyclone V devices?

Environment

  • Reset
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description The minimum pulse width for the Hard Processor System cold and warm resets (nPOR, nRST)  is 6 oscilator 1 (osc1) clock cycles on Cyclone® V devices. The osc1 clock range is 10 - 50 MHz.
    Resolution This information will be added to the next version of the Cyclone V handbook.

    Related Products

    This article applies to 2 products

    Cyclone® V SE SoC FPGA
    Cyclone® V SX SoC FPGA

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