Article ID: 000084551 Content Type: Troubleshooting Last Reviewed: 06/30/2014

Is the DFE_control register a Read (R) or Write (W) location in Stratix V GX, GS, and GT devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The DFE_control register is a Read (R) only location in Stratix® V GX, GS, and GT devices.

This is incorrectly shown as RW in ver 1.7 of the Altera® Transceiver PHY IP Core User Guide. 

This will be updated in a future revision of the Altera Transceiver PHY IP Core User Guide.

Resolution

Related Products

This article applies to 3 products

Stratix® V GX FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.