Article ID: 000084476 Content Type: Troubleshooting Last Reviewed: 07/08/2015

Why does the Triple Speed Ethernet IP core fail to report collisions correctly when operating in half-duplex mode?

Environment

    Ethernet
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Description

The Triple Speed Ethernet (TSE) IP core may fail to correctly assert the EXCESS_COL (Bit 11) and LATE_COL (Bit 12) fields of the Command_Config register and the rx_err[5] collision error signal.

Resolution

This problem is scheduled to be fixed in a future release of the IP core.

Related Products

This article applies to 32 products

Cyclone® V GT FPGA
Cyclone® III FPGAs
Stratix® V GX FPGA
Cyclone® IV GX FPGA
Cyclone® II FPGA
Cyclone® V GX FPGA
Arria® V GZ FPGA
Stratix® V GS FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Arria® V GX FPGA
Stratix® V GT FPGA
Intel® Arria® 10 GT FPGA
Arria® V GT FPGA
Stratix® III FPGAs
Stratix® IV GX FPGA
Arria® II GX FPGA
Intel® Arria® 10 GX FPGA
Arria® II GZ FPGA
Stratix® IV GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Intel® Arria® 10 SX SoC FPGA
Arria® GX FPGA
Cyclone® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® IV E FPGA
Arria® V ST SoC FPGA
Cyclone® III LS FPGA
Stratix® IV E FPGA
Arria® V SX SoC FPGA

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