Article ID: 000084315 Content Type: Error Messages Last Reviewed: 02/12/2013

Error (10149): Verilog HDL Declaration error at core_debug.sv(1): identifier "seq_core_debug_pkg" is already declared in the present scope

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This analysis and synthesis error message may be seen in the UniPHY example project when the UniPHY IP has these combination of settings :

    1) PHY Settings : Any of the PLL/DLL/OCT sharing mode options set to master or slave   

    2) Diagnostics : Enable EMIF On-Chip Debug Toolkit selected 

    The error is due to the file core_debug.sv being listed twice in the example design .qip file

    Resolution

    The workaround is to comment out one of the files in the example design .qip file. For example :

    #set_global_assignment -library "<IP_name>_example" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "<IP_name>_example/submodules/<IP_name>_example_if0_s0_software/core_debug.sv"]

    This issue will be fixed in a future version of Quartus® II.

    Related Products

    This article applies to 3 products

    Stratix® V GX FPGA
    Stratix® V GS FPGA
    Stratix® V E FPGA

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