Article ID: 000084272 Content Type: Troubleshooting Last Reviewed: 01/06/2014

Why does the ALTECC decoder simulation have glitches when the parity bit is incorrect?

Environment

  • Quartus® II Subscription Edition
  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In the Quartus II software version 12.1 SP1 and later, on the output of the ALTECC decoder megafunction you may see glitches on the parity bit for all single-bit errors. 

    Resolution

    To work around this problem, add one pipeline stage on the decoding result by setting output latency of 1 clock cycle in ALTECC wizard.

    Related Products

    This article applies to 1 products

    Stratix® V GX FPGA

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