Description
As indicated in On-Line Help, this error message means that your VHDL code uses an expression with the specified number of elements. However, the expression is required to have a different number of elements (the required number of elements is also specified in the message text). This often occurs if your signal widths are mismatched within the code. The line number indicates the location of the expression.
The Quartus® II software versions lower than 2.1 did not give you an error for these kind of illegal expressions. Therefore, you may see this error with older code that compiled sucessfully in a version prior to 2.1 because the code may have relied on the Compiler not to give an error for these cases. Mismatched signal widths, however, are not supported in the VHDL language, and other third-party synthesis tools will produce an error for this type of coding style as well. You must correct your VHDL code to fix this problem and eliminate the error message during compilation.