Regenerating Underlying PHY IP Cores in 40GbE and 100GbE MAC and PHY IP Cores

The 40GbE and 100GbE MAC and PHY IP cores include PHY IP cores generated by the MegaWizard Plug-In Manager. When regenerating PHY IP cores with a later Quartus II software revision, you may not be able to open the existing MegaWizard-generated file and regenerate it.

This issue is fixed in the 12.1 Quartus software release of the IP core.

For the 12.0 release of the IP core, Verilog files generated by the MegaWizard Plug-In Manager contain a known header comment in the first line of the file that the MegaWizard recognizes. In the 12.0 Quartus II software release, PMA files generated by the MegaWizard Plug-In Manager are appended with a standard comment set that is not recognized. Modify the headers of the MegaWizard-generated file so that the first line is a recognizable comment, such as:

You can then open and regenerate the existing MegaWizard-generated file.

The 40GbE PHY IP synthesis and simulation files are located at:

• (Synthesis files) <project_dir>/alt_eth_40g/quartus_synth/rtl_src/phy/pma_sv/alt_e40_e4x10/alt_e40_e4x10.v
• (Simulation files) <project_dir>/alt_eth_40g/sim_verilog/<SIMULATOR_NAME>/rtl_src/phy/pma_sv/alt_e40_e4x10/alt_e40_e4x10.v

The 100GbE PHY IP synthesis and simulation files are located at:

• (Synthesis files) <project_dir>/alt_eth_100g/quartus_synth/rtl_src/phy/pma_sv/alt_e100_e10x10/alt_e100_e10x10.v
• (Simulation files) <project_dir>/alt_eth_100g/sim_verilog/<SIMULATOR_NAME>/rtl_src/phy/pma_sv/alt_e100_e10x10/alt_e100_e10x10.v

Note that the <SIMULATOR_NAME> variable refers to Cadence, Mentor, or Synopsis. The PHY IP files must be updated with the correct header and edited in the MegaWizard in both the synthesis file set and the file set for the simulator you are using. Updating the PHY IP configuration in one of the file sets will not be automatically reflected in the other file set(s).