Why does the External Memory Interfaces Intel® Arria® 10 FPGA IP remain in reset during the second RTL simulation run when using the Abstract PHY ?

In the External Memory Interfaces Intel® Arria® 10 FPGA IP parameter editor Diagnostics tab, the Abstract PHY option can be selected to speed up the RTL simulation of the External Memory Interfaces Intel® Arria® 10 FPGA IP.

During the first simulation run, the altera_emif_nios_force_abphy.sv file is updated with signal forces to implement the PHY calibration.

When the first simulation run has completed, you must recompile the simulation fileset before you re-run the simulation.

If you do not recompile the fileset before running the simulation, the PHY will appear to stay in reset even if it's input global_reset_n signal has been de-asserted.