Article ID: 000084233 Content Type: Troubleshooting Last Reviewed: 01/26/2016

Why does the Arria 10 EMIF IP remain in reset during the second RTL simulation run when using the Abstract PHY ?

Environment

  • Quartus® II Subscription Edition
  • Reset
  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In the Arria® 10 External Memory Interfaces Parameter GUI Diagnostics tab, the Abstract PHY option can be selected to speed up the RTL simulation of the Arria 10 EMIF IP.

    During the first simulation run, the file altera_emif_nios_force_abphy.sv is updated with signal forces to implement the PHY calibration.

    Resolution

    When the first simulation run has completed, users must recompile the simulation fileset before re-running the simulation.

    If you don't recompile the fileset before re-running the simulation, the PHY will appear to stay in reset even if it's input global_reset_n signal has been de-asserted.

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 GX FPGA
    Intel® Arria® 10 SX SoC FPGA

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