1) Locate your PLL either in the design or in the project hierarchy.
2) Right click on the PLL and choose "Locate in Chip Editor". The PLL will be shown in the Chip Editor view.
3) Right click on the PLL in the Chip Editor and choose "Locate in Resource Property Editor", or double click on the PLL in the Chip Editor. The Resource Property Editor window opens with all of the post compilation PLL parameters.
4) The Properties/Modes section has all of the parameters that are available to change shown in white. Properties that cannot be modified are in gray. Double click on any parameter you wish to change and type the new value in that row.
5) After you change a parameter and click out of that field, or hit the return key, any PLL parameter (s) affected by that change will be shown highlighted in blue text with the new expected value.
6) Once you have completed your changes, save and check the netlist by clicking on the "check and save all netlist changes" icon in the vertical tool bar, or choose that option in the Edit menu.
7) The PLL will now be checked against the fitter algorithms for PLL operation. The message window will display any relevant information such as warnings or errors regarding your new PLL settings.
8) Run the assembler portion of the compiler tool. This will create a new SOF and POF for the project.
9) Run the timing analyzer to check the entire design with the PLL changes and verify correct operation using a timing simulation.
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