Description
The Quartus® II software can recognize and encode Verilog HDL and VHDL state machines (sequential circuits that advance through a number of states) during synthesis. However, there are certain coding styles that will cause HDL code to be synthesized as generic logic instead of inferring a state machine.
Refer to the Recommended HDL Coding Styles (PDF) chapter of the Quartus II handbook for Verilog HDL and VHDL coding guidelines that will ensure your state machine is inferred correctly in the Quartus II software.