Description
In the True-LVDS implementation, there are three frequencies that need to be managed: the clock frequency, the SERDES first-in first-out (FIFO) frequency, and the core frequency. In APEX 20KE devices, the clock multiplication factor and the SERDES factors must be the same, since this factor is used to generate the required SERDES FIFO and core frequencies from the LVDS input clock. This limits the APEX 20KE input LVDS clock frequency to a single, specific frequency.
With independent clock multiplication in Mercury and APEX II devices, the SERDES factor is independent of the LVDS phase-locked loop (PLL) multiplication factor. This simplifies the design by not limiting the designer to a single clock frequency since the clock multiplication factor can be set independent of the SERDES factor. For example, 622 Mbps data can be received with a 311 MHz clock and can be driven into the logic array as an 8-bit 77.75-MHz bus. Independent clock multiplication also enables high-speed I/O interfaces such as RapidIO and POS-PHY Level 4.