Below is a description of how the Quartus® Prime Design Software, IP cores, and Questa*-Intel® FPGA Edition Software utilize licenses:
Quartus® Prime Design Software:
All Quartus® Prime Design Software processes check for a valid license, including the Quartus® GUI, Analysis & Synthesis, Assembler, and TimeQuest Timing Analyzer. These processes start only if a valid license is available. They do not hold or occupy the license; they only validate that one is available.
However, the Fitter checks out a license when it starts and holds it for the duration of the Fitter process.
IP cores:
A license for an IP core is checked out when the Quartus® Prime Design Software opens the first encrypted file of the IP core for synthesis. This license is held for the duration of synthesis.
The Assembler checks out the license for every IP core to create the programming file and holds it for the duration of the Assembler process.
Questa*-Intel® FPGA Edition software:
Once Questa*-Intel® FPGA Edition Software loads a design unit during elaboration, a Questa-Intel® FPGA Edition license is checked out. It remains checked out until the simulation ends (quit -sim), or the simulator is closed.
Once a waveform is loaded into the simulator, a Questa*-Intel® FPGA Edition Software license is also checked out for viewing Wave Log Format File (.wlf), and it remains checked out until the waveform window is closed.