The second, and subsequent, devices in the chain will become active as soon as the nCEO signal of the previous device goes low. However, the nCEO signal from the preceding device does not necessarily become active on the byte boundary. If the user configuration data is not valid on the first DCLK edge following nCEO going low, then the device will latch incorrect data and never achieve successful configuration. This situation will only arise in situations where the user is sharing the bus on which the configuration data is presented such that the configuration data is only valid for a portion of the byte period.
Similarly the RDYnBSY line of the second device will go low on the first clock edge after the NCEO goes low, indicating data has been latched into the device. Hence RDYnBSY may not transition on the byte boundary for the second and subsequent devices in the chain.
The specific location of the nCEO transition within the byte is not defined in AN116. Only Stratix devices guarantee the nCEO transition falls on a byte boundary, all other devices may transition mid-byte.
This problem can be resolved by ensuring that the second device sees correct configuration data on the first rising edge of DCLK after the nCEO signal goes low. This can be achieved by delaying the nCEO signal by using external registers or an external RC network, or by presenting the next byte of data after the nCEO transition.