Article ID: 000083609 Content Type: Error Messages Last Reviewed: 12/23/2014

Error (129029): Input port CLK on atom "<DLL instance>", which is a arriav_dll primitive, is not connected to a valid source File: /dll.v Line: 53

Environment

  • Quartus® II Subscription Edition
  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The PLL output cannot be connected to the DLL directly when Enable access to dynamic phase shift ports is selected in the Altera PLL MegaWizard™ GUI. The Quartus® II software tries to insert the pll_dll_output atom between the PLL and DLL and causes the above fitter error.

    Resolution

    To work around this issue, insert the pll_dll_output atom as shown below:

    arriav_pll_dll_output arriav_pll_dll_output_test(
    .cclk(from_pll_outclk_0),
    .clkin(1\'b0),
    .clkout(to_dll_clk0)
    );

    Related Products

    This article applies to 5 products

    Arria® V GT FPGA
    Arria® V GX FPGA
    Arria® V GZ FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA

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