Description
In the Synplify software versions earlier than 2009.12, synthesis inserts TRI1 I/O primitives for unconnected output ports. This occurs even when the "Disable I/O Insertion" option is selected from the Device tab of the Implementation Options page in Synplify. When the netlist is brought into the Quartus® II software, these TRI1 primitives prevent virtual pin assignments from being honored. This may cause problems during fitting if the number of actual I/O plus the number of unconnected ports exceeds the capacity of the device.
In the Synplify software version 2009.12 and later, the unused output ports are left unconected when "Disable I/O Insertion" is turned on.
To work around this problem in earlier versions, do one of the following:
- Edit the HDL code to remove the unconnected output ports before running Synplify synthesis.
- Compile the design using the Quartus II integrated synthesis and assign the unconnected ports as virtual pins.