Article ID: 000083440 Content Type: Troubleshooting Last Reviewed: 06/25/2018

Why are the transceivers not reset correctly when using the Interlaken (2nd Generation) Intel® FPGA IP on Intel® Stratix® 10 FPGA?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interlaken (2nd Generation) Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime software version 18.0 and earlier, asserting the reset_n signal on the Interlaken (2nd Generation) Intel FPGA IP will not reset the transceivers contained within the core. 

    Resolution

    To work around this problem, manually connect the reset_n signal within the cleartext wrapper ilk_uflex_ext module contained in the IP core as shown below:

    Original Code:

    uflex_ilk_hard_pcs_xcvr #(

        .NUM_LANES (NUM_LANES),

        ...

        )C2_XCVR(

        //reset controller

        .mm_clk (mm_clk), //75-125 MHz

        .reset_n,

        ...

    Workaround Code:

        ...

        ) C2_xcvr (

        //reset controller

        .mm_clk (mm_clk), //75-125 MHz

        .reset_n (reset_n),

        ...

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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