Article ID: 000083381 Content Type: Troubleshooting Last Reviewed: 03/13/2017

The software design constraints (SDC) provided by the 10GBASE-R IP is invalid when the IP is instantiated within the VHDL generate block.

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

When the 10GBASE-R IP is instantiated within the VHDL generate block, the SDC provided by the IP is invalid. This issue affects all VHDL designs that instantiate the IP within the VHDL generate block.

Resolution

None

This issue will be fixed in a future version of the Quartus® Prime Standard Edition software.

Related Products

This article applies to 1 products

Intel® Programmable Devices

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.