Article ID: 000083327 Content Type: Troubleshooting Last Reviewed: 09/10/2018

Why does the Intel® Arria® 10 Hard IP for PCI* Express in Root Port mode, LTSSM not stay in the Disabled state when Link Disable bit is set to 1.

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    When software sets the Link Disable bit in the Link Control register, the Root Port LTSSM is directed to the Disabled state. Once it enters the Disabled state, it should stay in that state unless the software resets the Link Disable bit.
    However, when using the Intel® Arria® 10 Hard IP for PCI* Express, the Root Port exits the Disabled state even if the Link Disable bit is set.  

    Resolution

    There is no workaround for this problem. This problem not scheduled to be fixed.

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