Article ID: 000083264 Content Type: Troubleshooting Last Reviewed: 03/22/2023

Why is the "Additional CK/CK# phase" option grayed out in the parameter editor for Stratix® V and Arria® V GZ devices?

Environment

    Quartus® II Subscription Edition
    DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
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Description

The "Additional CK/CK# phase" option is grayed out in the parameter editor because custom phase shifts for the memory clock is not supported for that device and protocol.

Resolution

The Stratix® V and Arria® V GZ devices only support this option for UniPHY-based DDR2 memory controllers with a frequency of 150 MHz or above. 

Related Products

This article applies to 5 products

Stratix® V GT FPGA
Arria® V GZ FPGA
Stratix® V GX FPGA
Stratix® V GS FPGA
Stratix® V E FPGA

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