Article ID: 000083206 Content Type: Product Information & Documentation Last Reviewed: 12/19/2018

How can I change Base Address Register(BAR) Size when using the Avalon -MM Arria® V Hard IP for PCI Express* Intel® FPGA IP or the Avalon -MM Cyclone® V Hard IP for PCI Express* Intel® FPGA IP?

Environment

  • Cyclone® V FPGAs and SoC FPGAs
  • Arria® V FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Cyclone® V Hard IP for PCI Express Intel® FPGA IP
  • Arria® V Hard IP for PCI Express Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When using the Avalon -MM Arria® V Hard IP for PCI Express* Intel® FPGA IP or the Avalon -MM Cyclone® V Hard IP for PCI Express* Intel® FPGA IP, the BAR size in the GUI may appear fixed and set at "N/A".

    The BAR size when using Avalon - MM configuration of the IP is automatically set by Platform Designer and is not manually set by the user.

    Resolution

    To correctly set the required BAR size:

    First add the IP to Platform Designer and enable any required BAR Registers.

    Second, in Platform Designer, connect the BAR Register ports to the required other components within the design.

    If the PCIe* IP is then re-opened, you will see that the BAR size has been automatically set based on the connected componets.

    The BAR size cannot be manually set by the user.

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