Article ID: 000083200 Content Type: Product Information & Documentation Last Reviewed: 12/12/2018

How do non-posted tag requests work in the Intel® Arria® 10 Avalon®-ST Interface with SR-IOV PCI Express* core when more than one Physical Function is enabled?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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Description

When using the Intel® Arria® 10 Avalon®-ST Interface with SR-IOV PCI Express* core with more than one Physical Function enabled, the pool of tags for non-posted requests is shared across all the enabled Physical Functions.

Resolution

This additional information is scheduled to be added in a future update to the user guide.

Related Products

This article applies to 1 products

Intel® Arria® 10 GX FPGA

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