Article ID: 000083200 Content Type: Product Information & Documentation Last Reviewed: 12/12/2018

How do non-posted tag requests work in the Intel® Arria® 10 Avalon®-ST Interface with SR-IOV PCI Express* core when more than one Physical Function is enabled?

Environment

  • Intel® Arria® 10 GX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When using the Intel® Arria® 10 Avalon®-ST Interface with SR-IOV PCI Express* core with more than one Physical Function enabled, the pool of tags for non-posted requests is shared across all the enabled Physical Functions.

    Resolution

    This additional information is scheduled to be added in a future update to the user guide.

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