Article ID: 000083092 Content Type: Troubleshooting Last Reviewed: 02/21/2018

Why does the Low Latency Ethernet 10G MAC's dynamic generated example design has incorrect accuracy of 1588 latency figure?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
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    Critical Issue

    Description

    Due to a problem with Intel® Quartus® Prime version 16.0 and above, the Intel® Arria® 10 Low Latency Ethernet 10G MAC's dynamically generated multi-rate example design has additional /-3.2ns of error in 1588's accuracy. As a result, the total error may be larger than the user guide's claim, which is /-3ns.

     

    The following are the affected multi-rate example design variants:

    1. 1G/10G Ethernet with 1588 Example Design (Intel Arria 10)

    2. 10M/100M/1G/10G Ethernet with 1588 Example Design (Intel Arria 10)

    Resolution

    To work around this problem:

    1. For Intel Quartus Prime v16.0, after generated the affected example design, open altera_eth_multi_channel_1588.sv file from this directory  "<project_directory>\rtl" and modify the following lines to the correct figure as below: 

    localparam  DEFAULT_NSEC_PERIOD_10G     = 4'h3;                     

               localparam  DEFAULT_FNSEC_PERIOD_10G    = 16'h3333; 

    2. For Intel Quartus Prime v16.1 and above, after generated the affected example design, from Intel Quartus Prime menu, click “Open” and navigate to "<project_directory>\rtl\altera_eth_1588_tod" and select altera_eth_1588_tod_10g.ip to launch the IP Parameter Editor of Intel 10G 1588 Time-of-day module, and then update the following parameters to the correct figure as below:

               DEFAULT_NSEC_PERIOD to 3

               DEFAULT_FNSEC_PERIOD to 0x00003333

               DEFAULT_NSEC_ADJPERIOD to 3

               DEFAULT_FNSEC_ADJPERIOD to 0x00003333

    This problem is scheduled to be fixed in a future version of the Intel Quartus Prime software.

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