Article ID: 000083072 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Can the Synopsys Design Compiler FPGA (DC FPGA) software produce a gate-level simulation netlist after synthesis?

Environment

    Simulation
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Description

Yes, beginning with version 2005.06, the DC FPGA software can produce a post-synthesis gate-level simulation netlist when targeting Altera® device libraries.

 

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