Description
Due to a limitation in the Quartus® II software, port order in your source Verilog HDL netlist may not be maintained when the output Verilog HDL netlist is written out. Due to this limitation, if your testbench connects ports implicitly, you may see a mismatch between RTL and gate-level simulation.
Resolution
To work around this limitation, connect top-level ports explicitly in your Verilog HDL testbench.
This limitation is scheduled to be fixed in a future release of the Quartus II software.