Article ID: 000082659 Content Type: Troubleshooting Last Reviewed: 08/10/2015

L2 Cache Controller Revision Incorrectly Listed as r3p2

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Cortex-A9 Microprocessor Unit Subsystem chapter in Volume 3: Hard Processor System Technical Reference Manual of the Arria V Device Handbook and the Cyclone V Device Handbook incorrectly reports the revision number of the ARM CoreLink Level 2 Cache Controller L2C-310. This chapter reports the L2 cache controller revision as r3p2. The actual revision number of the L2 cache controller in these devices is r3p3.

    Resolution

    Update to v14.0 or later of the handbook. If you are looking at an earlier handbook, disregard the listed revision number.

    Related Products

    This article applies to 2 products

    Cyclone® V FPGAs and SoC FPGAs
    Arria® V FPGAs and SoC FPGAs

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